Vighnesh Iyer
Github, LinkedIn

I'm a PhD student in the EECS department at UC Berkeley advised by Prof. Bora Nikolic.

I work in the areas of design methodology, hardware modeling and verification, ML for DV, and power modeling. In the past, I have built a high-performance monadic RTL testbench API, designed a VIP and random generator library for a testing framework for Chisel circuits, built RTL coverage prediction models, and explored specification mining for bug localization.

Conference Reviews[Listing]

Misc Articles[Listing]

Research Topics[Listing]

Research Agenda

High performance testbench APIs and a SystemVerilog/UVM parity DV environment

Machine learning for coverage closure, bug hunting, constraint tuning, and regression suite construction + intelligent fuzzing

The first area is about demonstrating that verification can be more ergonomic and performant than the status quo. It is engineering focused, but still has many unanswered research questions.

The second area is research focused: we are working on techniques that may not pan out. ML has been very successful in continuous domain problems and learning fuzzy relationships, but not as successful in discrete domain problems with strict combinatorial relationships.